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rev. 1.7 4/15 copyright ? 2015 by silicon laboratories si823x si823x 0.5 and 4.0 a mp iso drivers (2.5 and 5 k v rms ) features applications safety approval description the si823x isolated driver family combines two independent, isolated drivers into a single package. th e si8230/1/3/4 are high-side/low-side drivers, and the si8232/ 5/6/7/8 are dual driver s. versions with peak output currents of 0.5 a (si8230/1/ 2/7) and 4.0 a (SI8233/4/5/6/8) are available. all drivers operate with a maximum supply voltage of 24 v. the si823x drivers utilize silicon l abs' proprietary silicon isolation technology, which provides up to 5 kv rms withstand voltage per ul1577 and fast 60 ns propagation times. driver outputs can be grounded to the same or separate grounds or connected to a positive or negative voltage. the ttl level compatible inputs with >400 mv hysteresis are available in individual control input (si8230/2/ 3/5/6/7/8) or pwm input (si8231/4) configurations. high integration, low propagation delay, small installed size, flexibility, and cost-effectivene ss make the si823x family ideal for a wide range of isolated mosfet/igbt gate drive applications. ? two completely isolated drivers in one package ?? up to 5 kv rms input-to-output isolation ?? up to 1500 v dc peak driver-to- driver differential voltage ? hs/ls and dual driver versions ? up to 8 mhz switching frequency ? 0.5 a peak output (si8230/1/2/7) ? 4.0 a peak output (SI8233/4/5/6/8) ? high electromagnetic immunity ? 60 ns propagation delay (max) ? independent hs and ls inputs or pwm input versions ? transient immunity >45 kv/s ? overlap protection and programmable dead time ? aec-q100 qualification ? wide operating range ?? ?40 to +125 c ? rohs-compliant packages ?? soic-16 wide body ?? soic-16 narrow body ?? lga-14 ? power delivery systems ? motor control systems ? isolated dc-dc power supplies ? lighting control systems ? plasma displays ? solar and industrial inverters ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation) ? vde certification conformity ?? iec 60747-5-5 (vde 0884 part 5) ?? en 60950-1 (reinforced insulation) ? cqc certification approval ?? gb4943.1 ordering information: see page 39.
si823x 2 rev. 1.7
si823x rev. 1.7 3 t able of c ontents section page 1. top-level block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.1. typical operating characteristics (0.5 amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2. typical operating characteristics (4.0 amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3. family overview and logic operation during star tup . . . . . . . . . . . . . . . . . . . . . . . 21 3.4. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.6. layout considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7. undervoltage locko ut operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8. programmable dead time and overlap protection . . . . . . . . . . . . . . . . . . . . . . . . . 28 4. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1. high-side/low-side driv er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2. dual driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.3. dual driver with thermally enhanced package (si8236) . . . . . . . . . . . . . . . . . . . . .31 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. package outline: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. land pattern: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9. package outline: 16-pi n narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10. land pattern: 16-pin narro w body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11. package outline: 14 ld lga (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12. land pattern: 14 ld lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13. package outline: 14 ld lga with thermal pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .50 14. land pattern: 14 ld lga with thermal pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.1. si823x top marking (16-pin wide body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.2. top marking explanati on (16-pin wide body soic ) . . . . . . . . . . . . . . . . . . . . . . . 52 15.3. si823x top marking (16-pin narrow body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.4. top marking explanati on (16-pin narrow body so ic) . . . . . . . . . . . . . . . . . . . . . . 53 15.5. si823x top marking (14 ld lga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15.6. top marking explana tion (14 ld lga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
si823x 4 rev. 1.7 1. top-level block diagrams figure 1. si8230/3 two-input high-side/low-side isolated drivers figure 2. si8231/4 single-input high-side/low-side isolated drivers si8230/3 uvlo uvlo gndi vib vddi via vdda voa gnda vob vddi vddi isolation vddi vddb gndb disable isolation uvlo dt control & overlap protection dt si8231/4 uvlo uvlo gndi vddi pwm vdda voa gnda vob vddi vddi isolation vddi vddb gndb disable isolation uvlo dt control & overlap protection dt lpwm lpwm
si823x rev. 1.7 5 figure 3. si8232/5/6/7/8 dual isolated drivers si8232/5/6/7/8 uvlo vdda voa gnda vob vddi isolation vddi vddb gndb uvlo via isolation uvlo gndi vib vddi vddi disable
si823x 6 rev. 1.7 2. electrical specifications table 1. electrical characteristics 1 2.7 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test condition min typ max unit dc specifications input-side power supply voltage vddi si8230/1/2/3/4/5/6 si8237/8 4.5 2.7 ? ? 5.5 5.5 v driver supply voltage vdda, vddb voltage between vdda and gnda, and vddb and gndb (see ?6. ordering guide? ) 6.5 ? 24 v input supply quiescent current iddi(q) si8230/2/3/5/6/7/8 ? 2 3 ma si8231/4 ? 3.5 5 ma output supply quiescent current idda(q), iddb(q) current per channel ? ? 3.0 ma input supply active current iddi input freq = 500 khz, no load ? 3.5 ? ma output supply active current idda iddb current per channel with input freq = 500 khz, no load ?6?ma input pin leakage current ivia, ivib, ipwm ?10 ? +10 a dc input pin leakage current idisable ?10 ? +10 a dc logic high input threshold vih 2.0 ? ? v logic low input threshold vil ? ? 0.8 v input hysteresis vi hyst si8230/1/2/3/4/5/6/7/8 400 450 ? mv logic high output voltage voah, vobh ioa, iob = ?1 ma (vdda /vddb) ? 0.04 ?? v logic low output voltage voal, vobl ioa, iob = 1 ma ? ? 0.04 v output short-circuit pulsed sink current ioa(scl), iob(scl) si8230/1/2/7, figure 4 ? 0.5 ? a SI8233/4/5/6/8, figure 4 ? 4.0 ? a output short-circuit pulsed source current ioa(sch), iob(sch) si8230/1/2/7, figure 5 ? 0.25 ? a SI8233/4/5/6/8, figure 5 ? 2.0 ? a output sink resistance r on(sink) si8230/1/2/7 ? 5.0 ? ? SI8233/4/5/6/8 ? 1.0 ? ? notes: 1. vdda = vddb = 12 v for 5, 8, and 10 v uvlo devices; vdda = vddb = 15 v for 12.5 v uvlo devices. 2. tdd is the minimum overlap time without tr iggering overlap protec tion (si8230/1/3/4 only). 3. the largest rdt resistor that can be used is 220 k ? ..
si823x rev. 1.7 7 output source resistance r on(source) si8230/1/2/7 ? 15 ? ? SI8233/4/5/6/8 ? 2.7 ? ? vddi undervoltage threshold vddi uv+ vddi rising (si8230/1/2/3/4/5/6) 3.60 4.0 4.45 v vddi undervoltage threshold vddi uv? vddi falling (si8230/1/2/3/4/5/6) 3.30 3.70 4.15 v vddi lockout hysteresis vddi hys (si8230/1/2/3/4/5/6) ? 250 ? mv vddi undervoltage threshold vddi uv+ vddi rising (si8237/8) 2.15 2.3 2.5 v vddi undervoltage threshold vddi uv? vddi falling (si8237/8) 2.10 2.22 2.40 v vddi lockout hysteresis vddi hys (si8237/8) ? 75 ? mv vdda, vddb undervoltage threshold vdda uv+ , vddb uv+ vdda, vddb rising 5v threshold see figure 37 on page 27. 5.20 5.80 6.30 v 8v threshold see figure 38 on page 27. 7.50 8.60 9.40 v 10 v threshold see figure 39 on page 27. 9.60 11.1 12.2 v 12.5 v threshold see figure 40 on page 27. 12.4 13.8 14.8 v vdda, vddb undervoltage threshold vdda uv? , vddb uv? vdda, vddb falling 5v threshold see figure 37 on page 27. 4.90 5.52 6.0 v 8v threshold see figure 38 on page 27. 7.20 8.10 8.70 v 10 v threshold see figure 39 on page 27. 9.40 10.1 10.9 v 12.5 v threshold see figure 40 on page 27. 11.6 12.8 13.8 v vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 5 v ? 280 ? mv vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 8 v ? 600 ? mv vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 10 v or 12.5 v ? 1000 ? mv table 1. electrical characteristics 1 (continued) 2.7 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test condition min typ max unit notes: 1. vdda = vddb = 12 v for 5, 8, and 10 v uvlo devices; vdda = vddb = 15 v for 12.5 v uvlo devices. 2. tdd is the minimum overlap time without tr iggering overlap protec tion (si8230/1/3/4 only). 3. the largest rdt resistor that can be used is 220 k ? ..
si823x 8 rev. 1.7 ac specifications minimum pulse width ? 10 ? ns propagation delay t phl , t plh cl = 200 pf ? 30 60 ns pulse width distortion |t plh - t phl | pwd ? ? 5.60 ns minimum overlap time 2 tdd dt = vddi, no-connect ? 0.4 ? ns programmed dead time 3 dt figure 42, rdt = 100 k ? 900 ? ns figure 42, rdt = 6 k ? 70 ? ns output rise and fall time t r ,t f c l = 200 pf (si8230/1/2/7) ? ? 20 ns c l = 200 pf (SI8233/4/5/6/8) ? ? 12 ns shutdown time from disable true t sd ??60 ns restart time from disable false t restart ??60 ns device start-up time t start time from vdd_ = vdd_uv+ to voa, vob = via, vib ??40s common mode transient immunity cmti via, vib, pwm = vddi or 0 v v cm = 1500 v (see figure 6) 20 45 ? kv/s table 1. electrical characteristics 1 (continued) 2.7 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test condition min typ max unit notes: 1. vdda = vddb = 12 v for 5, 8, and 10 v uvlo devices; vdda = vddb = 15 v for 12.5 v uvlo devices. 2. tdd is the minimum overlap time without tr iggering overlap protec tion (si8230/1/3/4 only). 3. the largest rdt resistor that can be used is 220 k ? ..
si823x rev. 1.7 9 2.1. test circuits figures 4, 5, and 6 depict sink current, source current, and common-mode transient immunity test circuits, respectively. figure 4. iol sink current test circuit figure 5. ioh source current test circuit input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 15 v in out vss vdd schottky 50 ns 200 ns measure input waveform gnd vddi vddi 8 v + _ input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 15 v in out vss vdd 50 ns 200 ns measure input waveform gnd vddi schottky vddi 5.5 v + _
si823x 10 rev. 1.7 figure 6. common mode transient immunity test circuit oscilloscope 5v isolated ? supply vdda voa gnda 12 ? v supply high voltage surge generator vcm ? surge output 100k high voltage differential probe vddb vob gndb dt gndi vddi input disable input ? signal switch input output isolated ? ground si823x
si823x rev. 1.7 11 table 2. regulatory information 1,2,3,4 csa the si823x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. 60601-1: up to 125 v rms reinforced insulation working voltage; up to 380 v rms basic insulation working voltage. vde the si823x is certified according to iec 60747-5-5. for more details, see file 5006301-4880-0001. 60747-5-5: up to 891 v peak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. ul the si823x is certified under ul15 77 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si823x is certified under gb49 43.1-2011. for more details, se e certificates cqc13001096106 and cqc13001096108. rated up to 600 v rms reinforced insulation wo rking voltage; up to 1000 v rms basic insulation working voltage. notes: 1. regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. 2. regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. 3. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. 4. for more information, see "6. ordering guide" on page 39.
si823x 12 rev. 1.7 table 3. insulation and safety-related specifications parameter symbol test condition value unit wbsoic-16 5kv rms wbsoic-16 nbsoic-16 2.5 kv rms 14 ld lga 2.5 kv rms 14 ld lga with pad 1.0 kv rms nominal air gap (clearance) 1 l(1o1) 8.0 8.0/4.01 3.5 1.75 mm nominal external tracking (creepage) 1 l(1o2) 8.0 8.0/4.01 3.5 1.75 mm minimum internal gap (internal clearance) 0.014 0.014 0.014 0.014 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 600 v erosion depth ed 0.019 0.019 0.021 0.021 mm resistance (input-output) 2 r io 10 12 10 12 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 1.4 1.4 1.4 1.4 pf input capacitance 3 c i 4.0 4.0 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in ?7. package outline: 16-pin wide body soic? , ?9. package outline: 16-pin narrow body soic? , ?11. package outline: 14 ld lga (5 x 5 mm)? , and ?13. package outline: 14 ld lga with th ermal pad (5 x 5 mm)? . vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-16 and 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and creepage minimum for co mponent level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic 16 and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si823x is conv erted into a 2-terminal device. pins 1?8 (1-7, 14 ld lga) are shorted together to form the first terminal and pins 9?16 (8-14, 14 ld lga) are s horted together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 4. iec 60664-1 (vde 0884 part 5) ratings parameter test condition specification wb soic-16 nb soic-16 14 ld lga 14 ld lga with pad basic isolation group material group i i i i installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv i-iv rated mains voltages < 300 v rms i-iv i-iii i-iii i-iii rated mains voltages < 400 v rms i-iiii-iii-iii-ii rated mains voltages < 600 v rms i-iii i-ii i-ii i-i
si823x rev. 1.7 13 table 5. iec 60747-5-5 insulation characteristics* parameter symbol test condition characteristic unit wb soic-16 nb soic-16 14 ld lga 14 ld lga with pad maximum working insulation voltage v iorm 891 560 373 v peak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1671 1050 700 v peak transient overvoltage v iotm t = 60 sec 6000 4000 2650 v peak pollution degree (din vde 0110, table 1) 222 insulation resistance at t s , v io =500v r s >10 9 >10 9 >10 9 ? *note: maintenance of the safety data is ensured by protective circuits. the si823x provides a climate classification of 40/125/21. table 6. iec safety limiting values 1 parameter symbol test condition wb soic-16 nb soic-16 14 ld lga 14 ld lga with pad unit case temperature t s 150 150 150 150 c safety input current i s ? ja = 100 c/w (wb soic-16), 105 c/w (nb soic-16, 14 ld lga), 50 c/w (14 ld lga with pad) v ddi =5.5v, v dda =v ddb =24v, t j =150c, t a =25c 50 50 50 100 ma device power dissipation 2 p d 1.2 1.2 1.2 1.2 w notes: 1. maximum value allowed in the event of a failure. re fer to the thermal derating curve in figures 7 and 8. 2. the si82xx is tested with v ddi =5.5v, v dda =v ddb =24v, t j =150oc, c l = 100 pf, input 2 mhz 50% duty cycle square wave.
si823x 14 rev. 1.7 table 7. thermal characteristics parameter symbol wb soic-16 nb soic-16 14 ld lga 14 ld lga with pad unit ic junction-to-air thermal resistance ? ja 100 105 105 50 c/w table 8. absolute maximum ratings 1 parameter symbol min max unit storage temperature 2 t stg ?65 +150 c ambient temperature under bias t a ?40 +125 c junction temperature t j ?+150 c input-side supply voltage vddi ?0.6 6.0 v driver-side supply voltage vdda, vddb ?0.6 30 v voltage on any pin with respect to ground v io ?0.5 vdd + 0.5 v peak output current (t pw = 10 s, duty cycle = 0.2%) (0.5 amp versions) i opk ?0.5 a peak output current (t pw = 10 s, duty cycle = 0.2%) (4.0 amp versions) i opk ?4.0 a lead solder temperature (10 sec.) ? 260 c maximum isolation (input to output) (1 sec) wb soic-16 ? 6500 v rms maximum isolation (output to output) (1 sec) wb soic-16 ? 2500 v rms maximum isolation (input to output) (1 sec) nb soic-16 ? 4500 v rms maximum isolation (output to output) (1 sec) nb soic-16 ? 2500 v rms maximum isolation (input to output) (1 sec) 14 ld lga without thermal pad ? 3850 v rms maximum isolation (output to output) (1 sec) 14 ld lga without thermal pad ?650v rms maximum isolation (input to output) (1 sec) 14 ld lga with thermal pad ? 1850 v rms maximum isolation (output to output) (1 sec) 14 ld lga with thermal pad ??0v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. vde certifies storage temperature from ?40 to 150 c.
si823x rev. 1.7 15 figure 7. wb soic-16, nb soic-16, 14 ld lga thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-5 figure 8. 14 ld lga with pad thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-5 0 200 150 100 50 60 40 20 0 case temperature (oc) safety-limiting current (ma) vddi = 5.5 v vdda, vddb = 24 v 10 30 50 0 200 150 100 50 120 80 40 0 case temperature (oc) safety-limiting current (ma) 20 60 100 vddi = 5.5 v vdda, vddb = 24 v
si823x 16 rev. 1.7 3. functional description the operation of an si823x channel is analogous to that of an opt ocoupler and gate driver, except an rf carrier is modulated instead of light. this simple architecture provid es a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si823x channel is shown in figure 9. figure 9. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 10 for more details. figure 10. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver dead time control 0.5 to 4 a peak gnd v dd driver input signal output signal modulation signal
si823x rev. 1.7 17 3.1. typical operati ng characteristics (0.5 amp) the typical performance characteristics depicted in figure s 11 through 22 are for information purposes only. refer to table 1 on page 6 for actual specification limits. figure 11. rise/fall time vs. supply voltage figure 12. propagation delay vs. supply voltage figure 13. supply current vs. supply voltage figure 14. supply current vs. supply voltage figure 15. supply current vs. temperature figure 16. rise/fall time vs. load 0 2 4 6 8 10 9 1215182124 rise/fall time (ns) vdda supply (v) vdd=12v, 25 c c l = 100 pf tfall trise 10 15 20 25 30 9 1215182124 propagation delay (ns) vdda supply (v) h-l l-h vdd=12v, 25 c c l = 100 pf 1 1.5 2 2.5 3 3.5 4 9141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 1 2 3 4 5 6 7 9141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1mhz 500khz 100khz 50 khz 1 2 3 4 5 -50 0 50 100 supply current (ma) temperature (c) vdda = 15v, f = 250khz, c l = 0 pf duty cycle = 50% 2 channels switching 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 rise/fall time (ns) load (nf) vdd=12v, 25 c tfall trise
si823x 18 rev. 1.7 figure 17. propagation delay vs. load figure 18. propagation delay vs. temperature figure 19. output sink current vs. supply voltage figure 20. output source current vs. supply voltage figure 21. output sink current vs. temperature figure 22. output source current vs. temperature 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 propagation delay (ns) load (nf) vdd=12v, 25 c h-l l-h 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 propagation delay (ns) temperature ( c) vdd=12v, load = 200pf h-l l-h ? ?? ? ?? ?? 10 12 14 16 18 20 22 24 6lqn&xuuhqwp$ 6xsso\9rowdjh9 vdd=12v, vout=5v ?? ? ??? ?? ?? e e?? e? 4? 10 15 20 25 6rxufh&xuuhqwp$ 6xsso\9rowdjh9 vdd=12v, vout=vdd-5v ?? ?? ?? ? ? 7 ?? ? ? ? ??? ?? -40 -10 20 50 80 110 6lqn&xuuhqwp$ 7hpshudwxuh & vdd=12v, vout=5v ?? ? ??5 ?? 3? e e?5 -40 -10 20 50 80 110 6rxufh&xuuhqwp$ 7hpshudwxuh & vdd=12v, vout=vdd-5v
si823x rev. 1.7 19 3.2. typical operati ng characteristics (4.0 amp) the typical performance characteristics depicted in figures 23 through 34 are for information purposes only. refer to table 1 on page 6 for actual specification limits. figure 23. rise/fall time vs. supply voltage figure 24. propagation delay vs. supply voltage figure 25. supply current vs. supply voltage figure 26. supply current vs. supply voltage figure 27. supply current vs. temperature figure 28. rise/fall time vs. load 0 2 4 6 8 10 9 1215182124 rise/fall time (ns) vdda supply (v) vdd=12v, 25 c c l = 100 pf tfall trise 10 15 20 25 30 9 1215182124 propagation delay (ns) vdda supply (v) h-l l-h vdd=12v, 25 c c l = 100 pf 0 2 4 6 8 10 12 14 9 1 41 92 4 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 2 4 6 8 10 12 14 9141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 2 4 6 8 10 -50 0 50 100 supply current (ma) temperature (c) vdda = 15v, f = 250khz, c l = 0 pf duty cycle = 50% 2 channels switching 0 5 10 15 20 25 30 35 40 012345678910 rise/fall time (ns) load (nf) vdd=12v, 25 c tfall trise
si823x 20 rev. 1.7 figure 29. propagation delay vs. load figure 30. propagation delay vs. temperature figure 31. output sink current vs. supply voltage figure 32. output source current vs. supply voltage figure 33. output sink current vs. temperature figure 34. output source current vs. temperature 10 15 20 25 30 35 40 45 50 012345678910 propagation delay (ns) load (nf) vdd=12v, 25 c h-l l-h 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 propagation delay (ns) temperature ( c) vdd=12v, load = 200pf h-l l-h 4 5 6 7 8 9 10 12 14 16 18 20 22 24 sink current (a) supply voltage (v) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 10 15 20 25 source current (a) supply voltage (v) vdd=12v, vout=vdd-5v 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 -40 -10 20 50 80 110 sink current (a) temperature ( c) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 -40 -10 20 50 80 110 source current (a) temperature ( c) vdd=12v, vout=vdd-5v
si823x rev. 1.7 21 3.3. family over view and logic operation during startup the si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations. 3.3.1. products table 9 shows the configuration and functional overview for each product in this family. 3.3.2. device behavior table 10 consists of truth tables for the si8230/3, si8231/4, an d si8232/5/6 families. table 9. si823x family overview part number configuration overlap protection programmable dead time inputs peak output current (a) si8230 high-side/low-side ?? via, vib 0.5 si8231 high-side/low-side ?? pwm 0.5 si8232/7 dual driver ? ? via, vib 0.5 SI8233 high-side/low-side ?? via, vib 4.0 si8234 high-side/low-side ?? pwm 4.0 si8235/6/8 dual driver ? ? via, vib 4.0 table 10. si823x family truth table 1 si8230/3 (high-side/low-side) truth table inputs vddi state disable output notes via vib voa vob llpoweredl ll output transition occurs after internal dead time expires. lhpoweredl lh output transition occurs after internal dead time expires. hlpoweredl hl output transition occurs after internal dead time expires. hhpoweredl l l invalid state. output transition occurs after internal dead time expires. x 2 x 2 unpowered x l l output returns to input state within 7 s of vddi power restoration. x x powered h l l device is disabled. si8231/4 (pwm input high-si de/low-side) truth table pwm input vddi state disable output notes voa vob h powered l h l output transition occurs after internal dead time expires. l powered l l h output transition occurs after internal dead time expires. x 2 unpowered x l l output returns to input state within 7 s of vddi power restoration. x powered h l l device is disabled. notes: 1. this truth table assumes vdda and vddb are powered. if vdda and vddb are below uvlo, see "3.7.2. undervoltage lockout" on page 26 for more information. 2. note that an input can power the input die through an internal diode if its source has adequate current.
si823x 22 rev. 1.7 si8232/5/6/7/8 (dual driver) truth table inputs vddi state disable output notes via vib voa vob llpoweredl ll output transition occurs immediately (no internal dead time). lhpoweredl lh output transition occurs immediately (no internal dead time). hlpoweredl hl output transition occurs immediately (no internal dead time). hhpoweredl hh output transition occurs immediately (no internal dead time). x 2 x 2 unpowered x l l output returns to input state within 7 s of vddi power restoration. x x powered h l l device is disabled. table 10. si823x family truth table 1 (continued) notes: 1. this truth table assumes vdda and vddb are powered. if vdda and vddb are below uvlo, see "3.7.2. undervoltage lockout" on page 26 for more information. 2. note that an input can power the input die through an internal diode if its source has adequate current.
si823x rev. 1.7 23 3.4. power supply connections isolation requirements mandate individual supplies fo r vddi, vdda, and vddb. the decoupling caps for these supplies must be placed as close to the vdd and gnd pi ns of the si823x as possible. the optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. low effective series resistance (esr) capacitors, such as tantalum, are recommended. 3.5. power dissipation considerations proper system design must assure that the si823x opera tes within safe thermal lim its across the entire load range.the si823x total power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, an d power dissipated by the series gate resistor and load. equation 1 shows total si823x power dissipation. equation 1. power dissipation example for 0.5 a driver using equation 1 with the following givens: v ddi =5.0v v dd2 =12v f=350khz r g =22 ? q g =25nc p d v ddi ?? i ddi ?? = 2i dd2 ?? v dd2 ?? f ?? q tl ?? v dd2 ?? r p r p r g + -------------------- f ?? q tl ?? v dd2 ?? r n r n r g + -------------------- 2fcintv dd2 2 ++++ where: p d is the total si823x device power dissipation (w) i ddi is the input-side maximum bias current (3 ma) i dd2 is the driver die maximum bias current (2.5 ma) c int is the internal parasitic capacitance (75 pf for the 0.5 a driver and 370 pf for the 4.0 a driver) v ddi is the input-side vdd supply voltage (2.7 to 5.5 v) v dd2 is the driver-side supply voltage (10 to 24 v) f is the switching frequency (hz) q tl is the total highside bootstrap charge (see section 2.2 of an486) r g is the external gate resistor r p is the r ds on ?? of the driver pull-up switch: (rp=15 ? for the 0.5a driver; rp=2.7 ? for the 4.0a driver) r n is the r ds on ?? of the driver pull-down switch: (rn=5 ? for the 0.5a driver and 1 ? for the 4.0a driver) pd 0.015 = 0.060 350 10 3 ? ?? 25 10 9 ? ? ?? 12 ?? 15 15 22 + ------------------- 350 10 3 ? ?? 25 10 9 ? ? ?? 12 ?? 5 522 + --------------- - 2 350 10 3 ? ?? 75 10 12 ? ? ?? 144 ?? ?? 145 mw from which the driver junction temperatur e is calculated using equation 2, where: pd is the total si823x device power dissipation (w) ? ja is the thermal resistance from junction to air (105 c/w in this example) t a is the ambient temperature = ++ + +
si823x 24 rev. 1.7 the maximum power dissipation allowable for the si823x is a function of the package thermal resistance, ambient temperature, and maximum allowable juncti on temperature, as shown in equation 2: equation 2. substituting values for p dmax t jmax , t a , and ? ja into equation 2 results in a maximum allowable total power dissipation of 1.19 w. maximum allowabl e load is found by substituting this limit and the appropriate data sheet values from table 1 on page 6 into equation 1 and si mplifying. the result is equation 3 (0.5 a driver) and equation 4 (4.0 a driver), both of which assume vddi = 5 v and vdda = vddb = 18 v. equation 3. equation 4. equation 3 and equation 4 are graphed in figure 35 where the points along the load line represent the package dissipation-limited value of cl for the corresponding switching frequency. t j p d ? ja ? t a = (0.145)(105) + 20 = 35.2 c + = p dmax t jmax t a ? ? ja --------------------------- where: p dmax = maximum si823x power dissipation (w) t jmax = si823x maximum junction temperature (150 c) t a = ambient temperature (c) ? ja = si823x junction-to-air thermal resistance (105 c/w) f = si823x switching frequency (hz) ? ? ? f -------------------------- 7.5 ? 10 11 ? ? = c l(max) 1.4 10 3 ? ? f -------------------------- 3.7 ? 10 10 ? ? =
si823x rev. 1.7 25 figure 35. max load vs. switching frequency 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000 100 150 200 250 300 350 400 450 500 550 600 650 700 frequency (khz) max load (pf) 0.5a driver (pf) 4a driver (pf)
si823x 26 rev. 1.7 3.6. layout considerations it is most important to minimize ringing in the drive path and noise on the si823x vdd lines. care must be taken to minimize parasitic inductance in these pa ths by locating the si823x as close to the device it is driving as possible. in addition, the vdd supply and ground trace paths must be kept short. for this re ason, the use of power and ground planes is highly recommended. a split ground plane system having separate ground and vdd planes for power devices and small signal components provides the best overall noise performance. 3.7. undervoltage lockout operation device behavior during start-up, normal operation and shutdown is shown in figure 36, where uvlo+ and uvlo- are the positive-going and negative-going thresholds respectively. note that outputs voa and vob default low when input side power su pply (vddi) is not present. 3.7.1. device startup outputs voa and vob are held low during power-up un til vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs via and vib. 3.7.2. undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. the input (control) side, driver a and driver b, each have their own undervoltage lockout monitors. the si823x input side enters uvlo when vddi < vddi uv? , and exits uvlo when vddi > vddi uv+ . the driver outputs, voa and vob, remain low when the input side of the si823x is in uvlo and their respective vdd supply (vdda, vddb) is within toler ance. each driver output can enter or ex it uvlo independently. for example, voa unconditionally enters uvlo when vdda falls below vdda uv? and exits uvlo when vdda rises above vdda uv+ . figure 36. device behavior during normal operation and shutdown via voa disable vddi uvlo- vdda tstart tstart tstart tsd trestart tphl tplh uvlo+ uvlo- uvlo+ tsd vdd hys vdd hys
si823x rev. 1.7 27 3.7.3. undervoltage lockout (uvlo) the uvlo circuit unconditionally drives vo low when vdd is below the lockout threshol d. referring to figures 37 through 40, upon power up, the si823x is main tained in uvlo unt il vdd rises above vdd uv+ . during power down, the si823x enters uvlo when vdd falls below th e uvlo threshold plus hy steresis (i.e., vdd < vdd uv+ ? vdd hys ). figure 37. si823x uvlo response (5 v) figure 38. si823x uvlo response (8 v) figure 39. si823x uvlo response (10 v) figure 40. si823x uvlo response (12.5 v) 3.5 10.5 v dduv+ (typ) output voltage (v o ) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 supply voltage (v dd - v ss ) (v) 6.0 10.5 v dduv+ (typ) output voltage (v o ) 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 supply voltage (v dd - v ss ) (v) 8.5 10.5 v dduv+ (typ) output voltage (v o ) 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 supply voltage (v dd - v ss ) (v) 11.3 10.5 v dduv+ (typ) output voltage (v o ) 11.8 12.3 12.8 13.3 13.8 14.3 14.8 15.3 supply voltage (v dd - v ss ) (v)
si823x 28 rev. 1.7 3.7.4. control inputs via, vib, and pwm inputs are high-true, ttl level-compatible logic inputs. a logic high signal on via or vib causes the corresponding output to go high. for pwm input versions (si8231/4), voa is high and vob is low when the pwm input is high, and voa is low and vob is high when the pwm input is low. 3.7.5. disable input when brought high, the disable input un conditionally drives voa and vob lo w regardless of th e states of via and vib. device operation term inates within tsd after disable = v ih and resumes within trestart after disable = v il . the disable input has no effect if vddi is below its uvlo level (i.e., voa, vob remain low). 3.8. programmable dead time and overlap protection all high-side/low-side drivers (si823 0/1/3/4) include programmable overlap protection to prevent outputs voa and vob from being high at the same time . these devices also include programm able dead time, which adds a user- programmable delay between transitions of voa and vob. when enabled, dead time is present on all transitions, even after overlap recovery. the amount of dead time delay (dt) is programmed by a single resistor (rdt) connected from the dt input to ground per equation 5. note that the dead time pin can be tied to vddi or left floating to provide a nominal dead time at approximately 400 ps. equation 5. the device driving via and vib should provide a minimum dead time of tdd to avoid activating overlap protection. input/output timing wa veforms for the two-input drivers are shown in figure 41, and dead time waveforms are shown in figure 42. figure 41. input / output waveforms for high-side / low-side two-input drivers dt 10 rdt where: ? dt dead time (ns) and rdt dead time programming resistor (k ?? = = ? via/ pwm vib voa vob a b c d e f g h i ref description a normal operation: vi a high, vib low. b normal operation: vi b high, via low. c contention: via = vib = high. d recovery from contention: via transitions low. e normal operation: via = vib = low. f normal operation: vi a high, vib low. g contention: via = vib = high. h recovery from contention: vib transitions low. i normal operation: vib transitions high.
si823x rev. 1.7 29 figure 42. dead time waveforms for high-side/low-side two-input drivers via/ pwm vib voa vob dt dt 10% 10% 90% 90% 50% vob a. typical dead time operation via/ pwm voa vob dt dt vib dt dt overlap overlap b. dead time operation during overlap
si823x 30 rev. 1.7 4. applications the following examples illustrate typical circuit configurations using the si823x. 4.1. high-side/low-side driver figure 43a shows the si8230/3 controlled using the via an d vib input signals, and figure 43b shows the si8231/4 controlled by a single pwm signal. figure 43. si823x in half-bridge application for both cases, d1 and cb form a conventional bootstrap circuit that allows voa to operate as a high-side driver for q1, which has a maximum drain voltage of 1500 v. the boot-strap start up time will depend on the cb cap chosen. see ?an486: high-side bootstrap design using si823x isodrivers in powe r delivery systems?. vob is connected as a conventional low-side driver, and, in most cases, vdd2 is the same as vddb. note that the input side of the si823x requires vdd in the range of 4.5 to 5. 5 v (2.7 to 5.5 v for si8237/8), while the vdda and vddb output side supplies must be between 6.5 and 24 v with re spect to their respective grounds. it is recommended that bypass capacitors of 0.1 and 1 f value be used on th e si823x input side and that they be located as close to the chip as possible. moreover, it is recommended that 0.1 and 10 f bypass capacitors, located as close to the chip as possible, be used on the si823x output side to reduce high-frequency noise and maximize performance. si8230/3 cb 1500 v max gndi vddi via vdda voa gnda vob vddi disable vdd2 dt rdt controller vib c1 1 f out1 out2 i/o q1 q2 d1 vddb c3 1 f si8231/4 cb pwm vdda voa gnda vob disable dt rdt controller pwmout i/o q1 q2 d1 ab vdd2 c3 1 f 1500 v max c2 0.1 f gndi vddi vddi c1 1 f c2 0.1 f vddb gndb c4 0.1 f c5 10 f vddb gndb c4 0.1 f c5 10 f
si823x rev. 1.7 31 4.2. dual driver figure 44 shows the si823x configured as a dual driver. note that the drain voltages of q1 and q2 can be referenced to a common ground or to different grounds with as much as 1500 v dc between them. figure 44. si8232/5/7/8 in a dual driver application because each output driver resides on its own die, the relative voltage polarities of voa and vob can reverse without damaging the driver. that is, the voltage at voa ca n be higher or lower than t hat of vob by vdd without damaging the driver. therefore, a dual driver in a low-si de high side/low side drive application can use either voa or vob as the high side driver. similarly, a dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes. 4.3. dual driver with the rmally enhanced package (si8236) the thermal pad of the si8236 must be connected to a he at spreader to lower thermal resistance. generally, the larger the thermal shield?s area, the lower the thermal resistance. it is recommended that thermal vias also be used to add mass to the shield. vias generally have much more mass than the shield alone and consume less space, thus reducing thermal resistance more effectively. while th e heat spreader is not generally a circuit ground, it is a good reference plane for the si8236 and is also useful as a shield layer for emi reduction. with a 10mm 2 thermal plane on the outer layers (including 20 thermal vias), the thermal impedance of the si8236 was measured at 50 c/w. this is a significant improv ement over the si8235 which does not include a thermal pad. the si8235?s thermal resistance was measured at 105 c /w. in addition, note that the gnda and gndb pins for the si8236 are connected together through the thermal pad. si8232/5/7/8 via vdda voa gnda vob vddb gndb disable controller vib ph1 ph2 i/o q1 q2 vdda vddb gndi vddi vddi c1 1 f c2 0.1 f c5 0.1 f c6 10 f c3 0.1 f c4 10 f
si823x 32 rev. 1.7 5. pin descriptions table 11. si8230/3 two-input hs/ls isolated driver (soic-16) pin name description 1 via non-inverting logic in put terminal for driver a. 2 vib non-inverting logic in put terminal for driver b. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input uncond itionally drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 400 ps dead time when con- nected to vddi or left open (see "3.8. programmable dead time and overlap protection" on page 28). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for driver b. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8230 SI8233 soic-16 (wide) via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8230 SI8233 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16
si823x rev. 1.7 33 table 12. si8231/4 pwm input hs/ls isolated driver (soic-16) pin name description 1 pwm pwm input. 2 nc no connection. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input uncond itionally drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 400 ps dead time when con- nected to vddi or left open (see "3.8. programmable dead time and overlap protection" on page 28). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for driver b. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8231 si8234 soic-16 (wide) pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8231 si8234 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16
si823x 34 rev. 1.7 table 13. si8232/5/7/8 dual isolated driver (soic-16) pin name description 1 via non-inverting logic inpu t terminal for driver a. 2 vib non-inverting logic inpu t terminal for driver b. 3 vddi input-side power supply terminal; connect to a so urce of 4.5 to 5.5 v, (2.7 to 5.5 v for si8237/8). 4 gndi input-side ground terminal. 5 disable device disable. w hen high, this inpu t unconditionally drives ou tputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 nc no connection. 7 nc no connection. 8 vddi input-side power supply terminal; connect to a so urce of 4.5 to 5.5 v, (2.7 to 5.5 v for si8237/8). 9 gndb ground terminal for driver b. 10 vob driver b output. 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output. 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. via nc vddi gndi disable nc vib vddi vdda voa gnda nc nc vddb vob gndb si8232 si8235 si8237 si8238 soic-16 (wide) via vib vddi gndi disable nc nc vddi vdda voa gnda nc nc vddb vob gndb si8232 si8235 si8237 si8238 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16
si823x rev. 1.7 35 table 14. SI8233 two-input hs/ls isolated driver (14 ld lga) pin name description gndi 1 input-side ground terminal. via 2 non-inverting logic in put terminal for driver a. vib 3 non-inverting logic in put terminal for driver b. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally dr ives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. dt 6 dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transiti ons of voa and vob. defaults to 400 ps dead time when connected to vddi or left open (see"3.8. programmable dead time and overlap protection" on page 28). vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. lga-14 (5 x 5 mm) gndi via vib vddi disable dt vddi vdda voa gnda nc vddb vob gndb SI8233 1 2 3 4 5 6 7 14 13 12 11 10 7 8
si823x 36 rev. 1.7 table 15. si8234 pwm input hs/ls isolated driver (14 ld lga) pin name description gndi 1 input-side ground terminal. pwm 2 pwm input. nc 3 no connection. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally dr ives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. dt 6 dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transiti ons of voa and vob. defaults to 400 ps dead time when connected to vddi or left open (see "3.8. programmable dead time and overlap protection" on page 28). vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. lga-14 (5 x 5 mm) gndi pwm nc vddi disable dt vddi vdda voa gnda nc vddb vob gndb si8234 1 2 3 4 5 6 7 14 13 12 11 10 7 8
si823x rev. 1.7 37 table 16. si8235 dual isolated driver (14 ld lga) pin name description gndi 1 input-side ground terminal. via 2 non-inverting logic in put terminal for driver a. vib 3 non-inverting logic in put terminal for driver b. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally dr ives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. nc 6 no connection. vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. lga-14 (5 x 5 mm) gndi via vib vddi disable nc vddi vdda voa gnda nc vddb vob gndb si8235 1 2 3 4 5 6 7 14 13 12 11 10 7 8
si823x 38 rev. 1.7 table 17. si8236 dual isolated driver (14 ld lga) pin name description gndi 1 input-side ground terminal. via 2 non-inverting logic in put terminal for driver a. vib 3 non-inverting logic in put terminal for driver b. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally dr ives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. nc 6 no connection. vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. gnda and gndb pins for the si8236 are connected together through the thermal pad. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. gnda and gndb pins for the si8236 are connected together through the thermal pad. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. lga-14 (5 x 5 mm) gndi via vib vddi disable nc vddi vdda voa gnda nc vddb vob gndb si8236 1 2 3 4 5 6 7 14 13 12 11 10 7 8
si823x rev. 1.7 39 6. ordering guide table 18. ordering part numbers 1,2 ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temperature range package type legacy ordering part number (opn) 2.5 kv only wide body (wb) package options si8230bb-d-is via, vib high side/ low side 0.5a 8v 2.5 kvrms ?40 to +125 c soic-16 wide body si8230-a-is si8231bb-d-is pwm high side/ low side si8231-a-is si8232bb-d-is via,vib dual driver si8232-a-is si8234cb-d-is pwm high side/ low side 4.0 a 10 v n/a SI8233bb-d-is via,vib high side/ low side 8v SI8233-b-is si8234bb-d-is pwm high side/ low side si8234-b-is si8235bb-d-is via,vib dual driver si8235-b-is si8230ab-d-is via, vib high side/ low side 0.5a 5v 2.5 kvrms ?40 to +125 c soic-16 wide body n/a si8231ab-d-is pwm n/a si8232ab-d-is via,vib dual driver n/a SI8233ab-d-is via,vib high side/ low side 4.0a 5v n/a si8234ab-d-is pwm n/a si8235ab-d-is via,vib dual driver n/a notes: 1. all packages are rohs-compliant with pea k reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. 2. ?si? and ?si? are used interchangeably.
si823x 40 rev. 1.7 narrow body (nb) package options si8230bb-d-is1 via,vib high side/ low side 0.5a 8v 2.5 kvrms ?40 to +125 c soic-16 narrow body n/a si8231bb-d-is1 pwm high side/ low side si8232bb-d-is1 via,vib dual driver SI8233bb-d-is1 via,vib high side/ low side 4.0a 8v si8234bb-d-is1 pwm high side/ low side si8235bb-d-is1 via,vib dual driver si8235ba-d-is1 via,vib dual driver 1.0 kvrms si8230ab-d-is1 via,vib high side/ low side 0.5a 5v 2.5 kvrms ?40 to +125 c soic-16 narrow body n/a si8231ab-d-is1 pwm n/a si8232ab-d-is1 via,vib dual driver n/a SI8233ab-d-is1 via,vib high side/ low side 4.0a 5v n/a si8234ab-d-is1 pwm n/a si8235ab-d-is1 via,vib dual driver n/a table 18. ordering part numbers 1,2 (continued) ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temperature range package type legacy ordering part number (opn) 2.5 kv only notes: 1. all packages are rohs-compliant with pea k reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. 2. ?si? and ?si? are used interchangeably.
si823x rev. 1.7 41 lga package options SI8233cb-d-im via,vib high side/ low side 4.0 a 10 v 2.5 kvrms ?40 to +125 c lga-14 5x5 mm n/a SI8233bb-d-im 8 v SI8233-b-im SI8233ab-d-im 5 v n/a si8234bb-d-im pwm 8 v si8234-b-im si8234ab-d-im 5 v n/a si8235bb-d-im via,vib dual driver 8 v si8235-b-im si8235ab-d-im 5 v n/a si8236ba-d-im 8 v 1.0 kvrms lga-14 5x5 mm with thermal pad si8236-b-im si8236aa-d-im 5v n/a 5 kv ordering options si8230bd-d-is via, vib high side/ low side 0.5 a 8 v 5.0 kvrms ?40 to +125 c soic-16 wide body n/a si8231bd-d-is pwm high side/ low side si8232bd-d-is via, vib dual driver SI8233bd-d-is via, vib high side/ low side 4.0 a si8234bd-d-is pwm high side/ low side si8235bd-d-is via, vib dual driver si8230ad-d-is via, vib high side/ low side 0.5a 5v 5.0 kvrms ?40 to +125 c soic-16 wide body n/a si8231ad-d-is pwm n/a si8232ad-d-is via, vib dual driver n/a SI8233ad-d-is via, vib high side/ low side 4.0a 5v n/a si8234ad-d-is pwm n/a si8235ad-d-is via, vib dual driver n/a 3 v vddi ordering options table 18. ordering part numbers 1,2 (continued) ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temperature range package type legacy ordering part number (opn) 2.5 kv only notes: 1. all packages are rohs-compliant with pea k reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. 2. ?si? and ?si? are used interchangeably.
si823x 42 rev. 1.7 si8237ab \d \ is1 via, vib dual driver 0.5 a 5v 2.5 kvrms 40 to +125 c soic-16 narrow body n/a si8237bb \d \is1 via, vib dual driver 8v si8238ab \d \ is1 via, vib dual driver 4.0 a 5v si8238bb \d \is1 via, vib dual driver 8v si8237ad \d \is via, vib dual driver 0.5 a 5v 5.0 kvrms soic-16 wide body si8237bd \ d \is via, vib dual driver 8v si8238ad \d \is via, vib dual driver 4.0 a 5v si8238bd \ d \is via, vib dual driver 8v table 18. ordering part numbers 1,2 (continued) ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temperature range package type legacy ordering part number (opn) 2.5 kv only notes: 1. all packages are rohs-compliant with pea k reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. 2. ?si? and ?si? are used interchangeably.
si823x rev. 1.7 43 7. package outline: 16-pin wide body soic figure 45 illustrates the package details for the si823x in a 16-pin wide body soic. table 19 lists the values for the dimensions shown in the illustration. figure 45. 16-pin wide body soic
si823x 44 rev. 1.7 table 19. package diagram dimensions dimension min max a ? 2.65 a1 0.10 0.30 a2 2.05 ? b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 ? 0 8 aaa ?0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation aa. 4. recommended reflow profile per je dec j-std-020 specification for small body, lead-free components.
si823x rev. 1.7 45 8. land pattern: 16 -pin wide body soic figure 46 illustrates the reco mmended land pattern details for the si823x in a 16-p in wide-body soic. table 20 lists the values for the dimens ions shown in the illustration. figure 46. 16-pin soic land pattern table 20. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si823x 46 rev. 1.7 9. package outline: 16 -pin narrow body soic figure 47 illustrates the package details for the si823x in a 16-pin narrow-body soic (so-16). table 21 lists the values for the di mensions shown in the illustration. figure 47. 16-pin small outline integrated circuit (soic) package table 21. package diagram dimensions dimension min max dimension min max a ? 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 ? h 0.25 0.50 b0 . 3 10 . 5 1 0 8 c 0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si823x rev. 1.7 47 10. land pattern: 1 6-pin narrow body soic figure 48 illustrates the recommended land pattern details for the si823x in a 16-pin narrow-body soic. table 22 lists the values for the dimens ions shown in the illustration. figure 48. 16-pin narrow body soic pcb land pattern table 22. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si823x 48 rev. 1.7 11. package outline: 14 ld lga (5 x 5 mm) figure 49 illustrates the package details for the si823x in an lga outline. table 23 lists the values for the dimensions shown in the illustration. figure 49. si823x lga outline table 23. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 0.25 0.30 0.35 d 5.00 bsc d1 4.15 bsc e 0.65 bsc e 5.00 bsc e1 3.90 bsc l 0.70 0.75 0.80 l1 0.05 0.10 0.15 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.15 eee ? ? 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si823x rev. 1.7 49 12. land pattern: 14 ld lga figure 50 illustrates the recomm ended land pattern deta ils for the si823x in a 14-pin lga. table 24 lists the values for the dimensions shown in the illustration. figure 50. 14-pin lga land pattern table 24. 14-pin lga land pattern dimensions dimension (mm) c1 4.20 e0 . 6 5 x1 0.80 y1 0.40 notes: general 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximu m material condit ion (mmc). least material condition (lmc) is ca lculated based on a fabrication allowance of 0.05 mm. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and elec tro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si823x 50 rev. 1.7 13. package outline: 14 ld lga with thermal pad (5 x 5 mm) figure 51 illustrates the package details fo r the si8236 isodriver in an lga out line. table 25 lists the values for the dimensions shown in the illustration. figure 51. si823x lga outline with thermal pad table 25. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 0.25 0.30 0.35 d 5.00 bsc d1 4.15 bsc e 0.65 bsc e 5.00 bsc e1 3.90 bsc l 0.70 0.75 0.80 l1 0.05 0.10 0.15 p1 1.40 1.45 1.50 p2 4.15 4.20 4.25 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.15 eee ? ? 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si823x rev. 1.7 51 14. land pattern: 14 ld lga with thermal pad figure 52 illustrates the recommended la nd pattern details for the si8236 in a 14-pin lga with thermal pad. table 26 lists the values for the di mensions shown in the illustration. figure 52. 14-pin lga with thermal pad land pattern table 26. 14-pin lga with thermal pad land pattern dimensions dimension (mm) c1 4.20 c2 1.50 d2 4.25 e0 . 6 5 x1 0.80 y1 0.40 notes: general: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximu m material condit ion (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design: 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 5. a stainless steel, laser-cut and elec tro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1. card assembly: 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si823x 52 rev. 1.7 15. top markings 15.1. si823x top marking (16-pin wide body soic) 15.2. top marking explanatio n (16-pin wide body soic) line 1 marking: base part number ordering options see ordering guide for more information. si823 = isodriver product series y = peak output current ? 0, 1, 2, 7 = 0.5 a ? 3, 4, 5, 8 = 4.0 a u = uvlo level ? a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating ? b = 2.5 kv; c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. line 3 marking: circle = 1.5 mm diameter (center justified) ?e4? pb-free symbol country of origin iso code abbreviation tw = taiwan si823yuv yywwtttttt tw e4
si823x rev. 1.7 53 15.3. si823x top marking (16-pin narrow body soic) 15.4. top marking explanatio n (16-pin narrow body soic) line 1 marking: base part number ordering options see ordering guide for more information. si823 = isodriver product series y = peak output current ? 0, 1, 2, 7 = 0.5 a ? 3, 4, 5, 8 = 4.0 a u = uvlo level ? a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating ? b = 2.5 kv; c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. si823yuv yywwtttttt e4
si823x 54 rev. 1.7 15.5. si823x top ma rking (14 ld lga) 15.6. top marking ex planation (14 ld lga) line 1 marking: base part number ordering options see ordering guide for more information. si823 = isodriver product series y = peak output current ? 0, 1, 2 = 0.5 a ? 3, 4, 5, 6 = 4.0 a line 2 marking: ordering options u = uvlo level ? a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating ? a = 1.0 kv; b = 2.5 kv; c = 3.75 kv; d = 5.0 kv i = ?40 to +125 c ambient temperature range m = lga package type line 3 marking: tttttt manufacturing code from assembly line 4 marking: circle = 1.5 mm diameter pin 1 identifier yyww manufacturing date code si823y uv-im tttttt yyww
si823x rev. 1.7 55 d ocument c hange l ist revision 0.11 to revision 0.2 ? updated all specs to reflec t latest silicon revision. ? updated table 1 on page 6 to include new uvlo options. ? updated table 8 on page 14 to reflect new maximum package isolation ratings ? added figures 34, 35, and 36. ? updated ordering guide to reflect new package offerings. ? added "3.7.3. undervoltage lockout (uvlo)" on page 27 to describe uvlo operation. revision 0.2 to revision 0.3 ? moved sections 2, 3, and 4 to after section 5. ? updated tables 14, 15, and 17. ?? removed si8230, si8231, and si8232 from pinout and from title. ? updated and added ordering guide footnotes. ? updated uvlo specifications in table 1 on page 6. ? added pwd and output supply active current specifications in table 1. ? updated and added typical operating condition graphs in "3.1. typical operating characteristics (0.5 amp)" on page 17 and "3.2. typical operating characteristics (4.0 amp)" on page 19. revision 0.3 to revision 1.0 ? updated tables 2, 3, 4, and 5. ? updated ?6. orde ring guide? . ?? added 5 v uvlo ordering options ? added device ma rking sections. revision 1.0 to revision 1.1 ? updated " features" on page 1. ?? updated cmti specification. ? updated table 1 on page 6. ?? updated cmti specification. ? updated table 5, ?iec 60747-5-5 insulation characteristics*,? on page 13. ? updated "4.2. dual driver" on page 31. ? updated "6. ordering guide" on page 39. ? replaced pin descriptions on page 1 with chip graphics. revision 1.1 to revision 1.2 ? updated "6. ordering guide" on page 39. ?? updated moisture sensitivity level (msl) for all package types. ? updated table 8 on page 14. ?? added junction temperature spec. ? updated table 2 on page 11 with new notes. ? added table 17 and pinout. ? updated figures 19, 20, 21, and 22 to reflect correct y-axis scaling. ? updated figure 44 on page 31. ? updated "4.3. dual driver with thermally enhanced package (si8236)" on page 31. ? updated "7. package outline: 16-pin wide body soic" on page 43. ? updated table 19, ?package diagram dimensions,? on page 44. ? change references to 1.5 kv rms rated devices to 1.0 kv rms throughout. ? updated "3.5. power dissipation considerations" on page 23. revision 1.2 to revision 1.3 ? added si8237/8 throughout. ? updated table 1 on page 6. ? updated figure 4 on page 9. ? updatedfigure 5 on page 9. ? added figure 6 on page 10. ? updated table 10 on page 21. ?? created notes 1 and 2. ? updated "3.8. programmable dead time and overlap protection" on page 28. ?? removed references to figures 26a and 26b. ? updated table 18 on page 39. ?? added si8235-ba-c-is1 ordering part number. ?? added table note. revision 1.3 to revision 1.4 ? updated "6. ordering guide" on page 39. ?? updated ? 3 v vddi ordering options? . revision 1.4 to revision 1.5 ? updated table 1, input and output supply current. ? added references to aec-q100 qualified throughout. ? changed all 60747-5-2 references to 60747-5-5. ? added references to cqc throughout. ? updated pin descriptions throughout. ?? corrected dead time default to 400 ps from 1 ns. ? updated table 18, ordering part numbers. ?? removed moisture sensitivity level table notes.
si823x 56 rev. 1.7 revision 1.5 to revision 1.6 ? updated table 18, ordering part numbers. ?? added revision d ordering part numbers. ?? removed all ordering part numbers of previous revisions. revision 1.6 to revision 1.7 ? updated table 2 on page 11 ?? added cqc certificate numbers. ? updated table 3 on page 12 ?? updated erosion depth. ? updated table 5 on page 13 ?? updated v pr for wbsoic-16. ? updated table 8 on page 14 ?? removed io and added peak output current specifications. ? updated equation 1 example on page 23. ? updated figure 43 on page 30. ? updated figure 44 on page 31. ? updated ordering guide table 18 on page 39. ?? removed note 2.
si823x rev. 1.7 57 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages.

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